Design-Reuse

How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs

Here we provide rational for using Centar’s floating-point IP core for the new Altera Arria 10 and Stratix 10 FPGA platforms. After a short contextual discussion section, a comparison of various FFT ...
EDN

FPGA-based FFT engine handles four times more input data

Rodger Hosking, Vice President, Richard Kuenzler, Engineer, Pentek Inc., Upper Saddle River, N.J. For years, field-programmable gate array (FPGA) technology has been a major cornerstone of board-level ...
Design-Reuse

Design and Implementation of an OCP-IP Compliant 64-Node Butterfly Network on Chip on Multi-FPGA

There is a growing demand of high-performance computing systems to cope with increasing data size and amount of arithmetic operation in various scientific computations. On top of this, several ...