Over the last twenty years, formal verification has grown from a niche technology practiced only by specialists to an essential part of mainstream chip development. Along the way, several advances ...

Design verification continues to consume the majority of engineering resources on today's ASIC and SOC design projects. Functional verification at the Register Transfer (RT) level, the process of ...

When we talk about the signoff of digital IP, we are referring to the full verification of a block. Every feature listed in a device’s datasheet requires verification. Furthermore, every register ...

Formal verification is being deployed more often and in more places in chip designs as the number of possible interactions grows, and as those chips are used in more critical applications. In the past ...

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...

In August 2023, the EEOC reached its first AI-bias settlement: $365,000 paid over a hiring algorithm that automatically rejected older applicants. Meanwhile, Europe’s new AI Act threatens fines of up ...

Formal methods represent a rigorous suite of mathematical techniques designed to specify, develop and verify system models with a high degree of reliability. In system modelling, these methods provide ...

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.