Hackaday

test pattern

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
EDN

Hierarchical test improves pattern application efficiency

For over 15 years, I've been a big proponent of hierarchical test. Hierarchical test is the commonly used term for creating DFT (design-for-test) features and test patterns at lower level circuit ...
Hackaday

Pocket-sized Test Pattern Generator Helps Check Those CRTs

Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one ...
Electronic Design

Reduce Test/Diagnosis Cost with Optimized Scan-Pattern Ordering

Download this article in PDF format. Finding the right balance among test cost, test quality, and data collection for running diagnosis requires consideration of several competing factors. Luckily ...
Electronic Design

Test Pattern Compression Saves Time and Bits

Test compression sounds like magic. Read on to learn how this trick is done. Large, complex ICs are viable because their design meets test as well as functional requirements. Design for test (DFT) was ...
EDN

Spectral content of NRZ test patterns

Many digital-communications systems use non-return-to-zero (NRZ) signaling, and system designers have created many NRZ test patterns to test and verify their products. These patterns usually either ...